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When there are no more frames in the transmit buffer and the transmit shift register is empty, the clock
stops, and communication ends. When the receiver is enabled, it samples data using the internal clock
when the transmitter transmits data. Operation of the RX and TX buffers is as in asynchronous mode.
16.3.3.3.1 Operation of USn_CS Pin
When operating in master mode, the USn_CS pin can have one of two functions, or it can be disabled.
If USn_CS is configured as an output, it can be used to automatically generate a chip select for a slave
by setting AUTOCS in USARTn_CTRL. If AUTOCS is set, USn_CS is activated when a transmission
begins, and deactivated directly after the last bit has been transmitted and there is no more data in the
transmit buffer. By default, USn_CS is active low, but its polarity can be inverted by setting CSINV in
USARTn_CTRL.
When USn_CS is configured as an input, it can be used by another master that wants control of the bus
to make the USART release it. When USn_CS is driven low, or high if CSINV is set, the interrupt flag
SSM in USARTn_IF is set, and if CSMA in USARTn_CTRL is set, the USART goes to slave mode.
16.3.3.4 Slave Mode
When the USART is in slave mode, data transmission is not controlled by the USART, but by an external
master. The USART is therefore not able to initiate a transmission, and has no control over the number
of bytes written to the master.
The output and input to the USART are also swapped when in slave mode, making the receiver take its
input from USn_TX (MOSI) and the transmitter drive USn_RX (MISO).
To transmit data when in slave mode, the slave must load data into the transmit buffer and enable the
transmitter. The data will remain in the USART until the master starts a transmission by pulling the
USn_CS input of the slave low and transmitting data. For every frame the master transmits to the slave,
a frame is transferred from the slave to the master. After a transmission, MISO remains in the same
state as the last bit transmitted. This also applies if the master transmits to the slave and the slave TX
buffer is empty.
If the transmitter is enabled in synchronous slave mode and the master starts transmission of a frame,
the underflow interrupt flag TXUF in USARTn_IF will be set if no data is available for transmission to
the master.
If the slave needs to control its own chip select signal, this can be achieved by clearing CSPEN in the
ROUTE register. The internal chip select signal can then be controlled through CSINV in the CTRL
register. The chip select signal will be CSINV inverted, i.e. if CSINV is cleared, the chip select is active
and vice versa.
16.3.3.5 Synchronous Half Duplex Communication
Half duplex communication in synchronous mode is very similar to half duplex communication in
asynchronous mode as detailed in Section 16.3.2.6 (p. 187) . The main difference is that in this mode,
the master must generate the bus clock even when it is not transmitting data, i.e. it must provide the
slave with a clock to receive data. To generate the bus clock, the master should transmit data with the
transmitter tristated, i.e. TXTRI in USARTn_STATUS set, when receiving data. If 2 bytes are expected
from the slave, then transmit 2 bytes with the transmitter tristated, and the slave uses the generated
bus clock to transmit data to the master. TXTRI can be set by setting the TXTRIEN command bit in
USARTn_CMD.
Note
When operating as SPI slave in half duplex mode, TX has to be tristated (not disabled)
during data reception if the slave is to transmit data in the current transfer.
2011-04-12 - d0001_Rev1.10
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